1. Field of the Invention
This invention is related to the field of semiconductor manufacturing, and more specifically, some embodiments relate to the creation of contours that represent the final image of the circuit on a wafer in a fashion that optimizes the yield of the circuit.
2. Description of the Invention
Integrated circuits are typically designed by starting with a functional description of the circuit that describes example the logical operations to be performed by the circuit. The design phase typically also includes a step in which the functional requirements are converted into a physical structure representation. Ultimately, the circuit is embodied in a physical structure that typically includes a number of layers, each layer having patterns which, when laid upon one another form the circuit. The patterns within each layer are most commonly represented through a GDS-file that primarily consists of rectangles or polygons. This representation is then used to perform a variety of checks that validate the desired functionality of the chip based on its structure as described by a GDS. However it is well known that these rectangles are a poor representation of the final shape of these structures on a wafer, especially in the subwavelength lithography domain, i.e that domain where the patterns formed are smaller than the wavelength of light used to image them. Accordingly, there are differences between the GDS representation and the actual physical embodiment of the circuit.
To aid in this process, several suppliers offer tools that predict wafer contours and are able to use them for functionality checks such as parasitic extraction. Examples of such tools include: The Mentor Technical Library: Computation of parasitic capacitances of an IC cell in accounting for photolithography effect; and The Synopsis Technical library (V. Malhotra et al. “Accurate parasitic extraction for Subwavelength Lithography”).
Another approach to optimization is one that optimizes the yield of a circuit in manufacturing by modifying the design to accommodate contour variations. This concept is generally defined as DFM (Design for Manufacturing). Yield generally refers to the portion of the total number of manufactured wafers (or die thereon) that satisfy to an adequate extent the functional or performance criteria established therefor. As the size of the features printed on a wafer has become smaller and smaller it has become increasingly more difficult to manufacture die with high yield. One of the factors with which the yield may be modified is through changes in the design. Common examples are modifying polygons to improve the printability by eliminating bridging and pinching sites. Yield of a layout may be improved by adding redundant vias so that electrical connections remain even if one of the vias in the connection fails. Overall chip leakage may be improved without significant impact on the highest possible chip frequency by selectively biasing gates.
A large number of companies are present in the EDA (electronic design automation) domain that have made public announcements on software for yield based design modifications. These companies are fore example Cadence®, Mentor Graphics®, Synopsys®, Takumi Technology, BLAZE™ DFM, Pyxis Technology, and Ponte, among others. A number of DFM tools are available by these companies. Cadence®, provides many EDA tools including a LPC (lithography process check) tool, CAA critical area analysis tool and CMP modeling to capture systematic metal thickness variations.
Mentor Graphics®, a provider of a variety of EDA tools has a product called Calibre® DFM. This program provides both yield analysis as well as yield improvement capabilities. For example the tool analyzes the exposure of the layout to via fails such as those where the contact connecting two layers is not patterned properly. The program automatically inserts redundant vias to minimize the exposure of the circuit to this yield loss mechanism. It is also capable of expanding and modifying polygons to provide for example better metal line via coverage. The program also analyzes to what extent a design complies with recommended design rules. These recommended design rules are put forward by the semiconductor manufacturer in an effort to improve yields. Typically, recommended ground rules are less aggressive and therefore less prone to failure during the manufacturing process.
Synopsys®, a provider of EDA tools uses a program called PrimeYield LCC to detect and correct potential manufacturing issues. The program provides an LCC (lithography compliance checker), model-based chemical mechanical polishing (CMP) and CAA, (critical area analysis). LCC provides CMP (checker for CMP variability). Tools for checking the severity of lithography and CMP induced variations. CAA critical area analysis checks for defect sensitivity of a layout. LCC detects potential lithography problems by calculating the expected wafer contours under different process conditions and detecting potential bridging and pinching sites. The tool also possesses an auto correction tool which automatically deals with some of these issues for example by adding space between lines, moving edges or corners. The CMP performs a model based analysis of metal layers for layout induced CMP variations that result in systematic line thickness variations. The resulting thickness map may be fed into the parasitic extraction tools for a more precise analysis of the chip performance. The CAA tools perform a analysis of the sensitivity of the layout to random defects that may cause opens or shorts.
Takumi Technology, a DFM startup provides tools for lithographic hotspot detection. It also provides a tool that detects layout that exhibit a high risk of failure to various yield loss mechanisms that include lithography driven fails. The tool provides repair suggestions, designs can also be fixed using an automatic repair tool. Blaze™ DFM takes into account timing and leakage considerations. It provides an annotated GDS for use in commercial OPC programs. Yield is improved for chips with stringent power consumption requirements. Ponte provides a model based yield assessment of a design.